? 2014 exar corporation xr81102 universal clock - high frequency lvpecl clock synthesizer exar.com/xr81102 rev 1b 1 / 8 general description the xr81101-ca02 is a clock synthesizer operating a t a 3.3v/2.5v supply with integer divider, using a 25mhz parallel resona nt crystal reference input provides a 125mhz lvpecl outputs. the device is optimi zed for use with a 25mhz crystal (or system clock) and generates a 125 mhz output clock for ge applications. the lvpecl outputs have very low ph ase noise jitter of sub 150fs, while consuming extremely low power. the application diagram below shows a typical synth esizer configuration with any standard crystal oscillating in fundamenta l mode. internal load capacitors are optionally available to minimize/eli minate external crystal loads. a system clock can also be used to overdrive the oscillator for a syn- chronous timing system. the typical phase noise plot below shows the jitter integrated over the 1.875mhz to 20mhz range that is widely used in wan systems. these clock devices show a very good high frequency noise floor below -150db. the xr81102 is a family of universal clock synthesize r devices in tssop- 8 packages. the devices generate any frequency in t he range of 100mhz to 1.5ghz by utilizing a highly flexible delta sigma modulator and a wide ranging vco. these devices can be used with standar d crystals or external system clock to support a wide variety of applicatio ns. this family of prod- ucts has an extremely low power pll block with core p ower consumption 40% less than the equivalent devices from competiti on. by second sourcing several of the existing sockets, these devices provi des a very compelling power efficiency value benefit across all market seg ments. other clock multiplier and/or driver configurations are possible in this clock family and can be requested from the factory features ? xr81102-ca02: factory configured ? one differential lvpecl output pair ? crystal oscillator interface which can also be overdriven using a single-ended reference clock ? output frequency: 125mhz ? crystal/input frequency: 25mhz, parallel resonant crystal ? rms phase jitter @ 125mhz, 1.875mhz - 20mhz: < 150fs ? full 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) package applications ? gigabit ethernet ? low-jitter clock generation ? synchronized clock systems ordering information C page 8 typical application v cc 2.5v or 3.3v q 125mhz v e e q oe xtal_in xtal_out 25mhz enable xr81102 r ca02 xr81102 phase noise (dbc/hz) 100hz 1khz 10khz 100 khz 1mhz 10mhz -120db -160db -140db -100db -80db -60db -180db -40db rms jitter = 120.9fs int range 1.875mhz to 20mhz
? 2014 exar corporation xr81102 2 / 8 exar.com/xr81102 rev 1b absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any maximum rating condition for extende d periods may affect device reliability and lifetime. supply voltage..................................... .....................+4.2v input voltage...................................... -0.5v to vcc + 0.5v output voltage...................................-0 .5v to vcc + 0.5v reference frequency/input crystal.........10mhz to 60mh z storage temperature................................ -55c to +125c lead temperature (soldering, 10 sec)............... ......300c esd rating (hbm - human body model)................. ...2kv operating conditions operating temperature range.....................-40 c to +85c
? 2014 exar corporation xr81102 3 / 8 exar.com/xr81102 rev 1b electrical characteristics unless otherwise noted: t a = -40c to +85c, v cc = 3.3v5% or 2.5v5%, v ee = 0v * limits applying over the full operating temperatu re range are denoted by a ?. symbol parameter conditions * min typ max units 3.3v power supply dc characteristics v cc power supply voltage ? 3.135 3.3 3.465 v i ee power supply current measured at 156.25mhz and inclu des the output load current 68 ma 2.5v power supply dc characteristics v cc power supply voltage ? 2.375 2.5 2.625 v i ee power supply current measured at 156.25mhz and inclu des the output load current 58 ma lvcmos/lvttl dc characteristics v ih input high voltage v cc = 3.465v ? 2.42 v cc + 0.3 v v cc = 2.625v ? 1.83 v cc + 0.3 v v il input low voltage v cc = 3.465v ? -0.3 1.03 v v cc = 2.625v ? -0.3 0.785 v i ih input high current (oe, fsel[1:0]) v in = v cc = 3.465v or 2.625v ? 15 a i il input low current (oe, fsel[1:0]) v in = 0v, v cc = 3.465v or 2.625v ? -10 a lvpecl dc characteristics v oh output high voltage ? v cc - 1.3 v cc - 0.4 v v ol output low voltage ? v cc - 2.0 v cc - 1.6 v v swing peak-to-peak output voltage swing ? 0.6 1.2 v crystal characteristics x mode mode of oscillations fundamental x f frequency 25 mhz esr equivalent series resistance 50 c s shunt capacitance 7 pf ac characteristics f out output frequency 125 mhz t jit ( i ) rms phase jitter 125mhz integration range 1.875mhz-20mhz 0.15 ps t jit (cc) cycle-to-cycle jitter using 25mhz, 18pf resonant crystal ? 10 ps t r /t f output rise/fall time 20% to 80% ? 100 500 ps odc output duty cycle ? 48 52 %
? 2014 exar corporation xr81102 4 / 8 exar.com/xr81102 rev 1b pin configuration pin assignments pin no. pin name type description 1 v cc supply power supply pin. 2 xtal_out output crystal oscillator output. 3 xtal_in input crystal oscillator input. 4 v ee supply negative supply pin. 5 oe input (900k : pull-up) output enable pin - lvcmos/lvttl active high input. outputs are enabled when oe = high. outputs are disabled when oe = low. 6 v cc supply power supply pin. 7 q output inverted lvpecl output. 8 q output positive lvpecl output. 13 4 5 6 7 8 2 xtal_out xtal_in q v cc v cc v ee oe q
? 2014 exar corporation xr81102 5 / 8 exar.com/xr81102 rev 1b functional block diagram typical performance characteristics figure 1 shows a typical phase noise performance plo t for a 125mhz clock output. the data was taken usi ng the industry standard agilent e5052b phase noise instrument. the integration range is 1.875mhz to 20mhz. figure 1: 125mhz operation, typical phase noise at 3.3v osc pdf & lpf vco divide by n divide by m q nq xtal_in xtal_out m/n = 5 oe
? 2014 exar corporation xr81102 6 / 8 exar.com/xr81102 rev 1b application information termination for lvpecl outputs the termination schemes shown in figure 2 and figure 3 are typical for lvpecl outputs. matched impedance l ayout techniques should be used for the lvpecl output pai rs to minimize any distortion that could impact your maxi mum operating frequency. figure 4 is an alternate termin ation scheme that uses a y-termination approach. figure 2: xr81102 3.3v lvpecl output termination figure 3: xr81102 2.5v lvpecl output termination figure 4: xr81102 alternate lvpecl output terminati on using y-termination output signal timing definitions the following diagrams clarify the common definitio ns of the ac timing measurements. figure 5: cycle-to-cycle jitter figure 6: output rise/fall time and swing figure 7: output period and duty cycle 3.3v 3.3v 3.3v 50 : 50 : 130 : 130 : 82 : 82 : lvpecl output lvpecl input 2.5v 2.5v 2.5v 50 : 50 : : : : : lvpecl output lvpecl input vcc vcc 50 : 50 : 50 : 50 : lvpecl output lvpecl input rtt for 3.3v systems rtt = 50 : for 2.5v systems rtt = 19 : q nq t cycle n t cycle n+1 t jit(cc) = |t cycle n - t cycle n+1| (over 1000 cycles) 20% 80% t r t f 80% 20% v swing q nq q nq t pw t period odc = x 100% t pw t period
? 2014 exar corporation xr81102 7 / 8 exar.com/xr81102 rev 1b mechanical dimensions 8-pin tssop note : the side, top and landing pattern drawings a re general to tssop packaging but the table is spec ific to the 8pin tssop t t t t
? 2014 exar corporation xr81102 8 / 8 exar.com/xr81102 rev 1b for further assistance: email: commtechsupport@exar.com exar technical documentation: http://www.exar.com/techdoc/ exar corporation headquarters and sales offices 48720 kato road tel: +1 (5 10) 668-7000 fremont, ca 95438 - usa fax: +1 (510) 66 8-7001 notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuit s described herein, conveys no license under any pat ent or other right, and makes no representation tha t the circuits are free of patent infringement. charts and schedules contai ned herein are only for illustration purposes and m ay vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracie s. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reaso nably be expected to cause failure of the life support system or to signi ficantly affect its safety or effectiveness. products are not authorized for use in such applications un less exar corporation receives, in writing, assurances to its satisfactio n that: (a) the risk of injury or damage has been mi nimized; (b) the user assumes all such risks; (c) p otential liability of exar cor- poration is adequately protected under the circumsta nces. reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. ordering information revision history part number package green operating temperature range shipping packaging marking xr81102-ca02-f 8-pin tssop yes -40c to +85c tube t02 xr81102-ca02tr-f 8-pin tssop yes -40c to +85c tape & reel t02 XR81102EVB eval board n/a n/a n/a n/a revision date description 1a april 2014 initial release. 1b april 28, 2014 update to general description. [ecn1421-16 l 05/25/2014]
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